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ddr2_sdram_latest[1].tar
- ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
ug_ddr_sdram
- DDR and DDR2 SDRAM Controller Compiler 的用户向导-DDR and DDR2 SDRAM Controller Compiler User Guide
sdram_controller_latest.tar
- This project implements a DDR2-SDRAM Controller on a Xilinx Spartan-3A Board
ddr2_v5
- 基于FPGA v5的ddr2-sdram控制器的设计verilog-Based on FPGA v5 of ddr2-sdram controller design verilog
DDR2_3(codePdoc)
- DDR2/3控制器的IP核及详细说明文档-DDR2/3 controller IP core and detailed documentation
DDR2_Control
- 本文档以Siga-S16 Spartan 6的FPGA开发板为例，为大家介绍用MIG工具生成DDR2控制器，并用ChipScope调试DDR2读写的方法。 -This document in the FPGA development board Siga-S16 Spartan 6 as an example, to introduce the formation of DDR2 controller with the MIG tool, and use the debug method of
test_ddr2_ip
- ddr2 SDRAM 高性能控制器及测试-DDR2 SDRAM High Performance Controller
ug_ddr_ddr2_sdram_hp
- ALTERA DDR2高性能控制器使用文档，包括存储控制器、用户接口、用户测试模块，各控制信号的说明。-ALTERA DDR2 high performance controller using a document, including the memory controller, user interface, user testing module, the control signal descr iption.
video_center_scan_scaler_alpha_blend
- 本工程实现两路视频信号阿尔法通道混合(alpha blend), 视频信号黑点中心 点扫描定位，期间用到视频帧缓存（frame cache）、视频信号缩放(scaler)等，且用到ram、DDR2等作为缓存，是很值得参考的视频图像处理工程。-scaler,alpha blend,ddr2 controller,center scan, frame cache, dpram, etc by verilog, include code and discr iption
codes
- my codes....................................................................................................
ddr2_controller
- A controller for DDR2 on FPGA with vhdl, content testbench, model and textfile-generation/data-detection using python.
DDR3-User-Guide
- 在DDR3内存控制器一起使用JESD79-3C符合标准SDRAM器件接口。内存类型，如DDR1 SDRAM，DDR2 SDRAM，SDR SDRAM，SBSRAM和异步不支持的回忆。在DDR3内存控制器，SDRAM，可用于程序和数据存储。梯形失真校正设备有一个实例。-Use JESD79-3C standard SDRAM DDR3 memory controller interface devices together. Memory types, such as DDR1 SDRAM, DD
t2_hpc
- 通过调用ddr2控制器，实现数据搬运功能，Verilog语言-ddr2 controller data handling capabilities
ddr
- ddr2控制器设计,适用于xilinx fpga,内含IP软核 -ddr2 controller design for xilinx fpga, embedded IP soft core
vip_ex2
- 特权同学开发板上的例程，DDR2控制器集成与读写测试(The routines on the privileged students' development board, DDR2 controller integration and reading and writing tests)